Method for fabricating semiconductor device and semiconductor device

ABSTRACT

Embodiments provide a method for fabricating a semiconductor device and the semiconductor device. The method includes: providing a semiconductor substrate having a first region and a second region; forming an initial mask layer on an upper surface of the substrate; patterning the initial mask layer, forming a first pattern mask having a first height on the first region, and forming a second pattern mask having a second height on the second region, where a pattern density of the first pattern mask is greater than a pattern density of the second pattern mask, and the first height is greater than the second height; and etching the substrate based on the first pattern mask and the second pattern mask, transferring a pattern of the first pattern mask to the first region, and transferring a pattern of the second pattern mask to the second region.

CROSSREFERENCE TO RELATED APPLICATION

This application claims priority to Chinese Patent Application No. 202111300177.X, titled “METHOD FOR FABRICATING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE” and filed to the State Patent Intellectual Property Office on Nov. 4, 2021, the entire contents of which are incorporated herein by reference.

TECHNICAL FIELD

The present disclosure relates to the field of integrated circuit and electronic component fabrication technology, and more particularly, to a method for fabricating a semiconductor device and the semiconductor device.

BACKGROUND

As a semiconductor memory device commonly used in computers, dynamic random access memory (DRAM) includes many repeated memory cells. Each memory cell generally includes a capacitor and a transistor. At present, in a stacked capacitor structure used in the DRAM, the capacitor is a cylinder capacitor having a higher aspect ratio, and a fabrication process employed to form the capacitor structure will directly affect performance of the capacitor structure.

SUMMARY

On this account, embodiments of the present disclosure provide a method for fabricating a semiconductor device and the semiconductor device.

According to a first aspect of the embodiments of the present disclosure, there is provided a method for fabricating a semiconductor device, comprising: providing a semiconductor substrate, the substrate having a first region and a second region; forming an initial mask layer on an upper surface of the substrate; patterning the initial mask layer, forming a first pattern mask having a first height on the first region, and forming a second pattern mask having a second height on the second region, a pattern density of the first pattern mask being greater than a pattern density of the second pattern mask, and the first height being greater than the second height; and etching the substrate based on the first pattern mask and the second pattern mask, transferring a pattern of the first pattern mask to the first region, and transferring a pattern of the second pattern mask to the second region.

According to a second aspect of the embodiments of the present disclosure, a semiconductor device is provided, where the semiconductor device is fabricated by means of the method for fabricating the semiconductor device, and the semiconductor device at least comprises a base substrate and a capacitor structure.

BRIEF DESCRIPTION OF THE DRAWINGS

In accompanying drawings (may be not drawn to scale), similar reference numerals may describe similar parts in different views. Similar reference numerals having different letter suffixes may denote different examples of similar parts. The accompanying drawings roughly show various embodiments discussed herein by way of examples instead of restriction manners.

FIGS. 1 a to 1 c are schematic structural diagrams showing processes of forming a semiconductor device according to one embodiment of the present disclosure;

FIG. 2 is a schematic flow diagram of a method for fabricating a semiconductor device according to another embodiment of the present disclosure;

FIGS. 3 a to 3 q are schematic structural diagrams showing processes of fabricating a semiconductor device according to one embodiment of the present disclosure; and

FIG. 4 is a cross-sectional view of a semiconductor device according to one embodiment of the present disclosure.

Reference numerals in the accompanying drawings:

100/200-base substrate; 101/201-stack structure; 101-1/B-peripheral region; 100-2/A-array region; 101 a-capacitor pattern; 102-first hard mask layer; 103-second hard mask layer; 102 a-first hard mask layer after first etching; 102 b-first hard mask layer after second etching; 200 a-contact structure; 200 b-insulating layer; 201 a-first sacrificial layer; 201 b/213-first support layer; 201 c-second sacrificial layer; 201 d/214-second support layer; 202-second initial mask layer; 202 a-first pattern mask; 202 b-second pattern mask; 203 a-first initial mask; 204-intermediate dielectric layer; 204 a-partial intermediate dielectric layer; 205-second mask layer; 205 a-dielectric anti-reflective coating; 205 b-bottom anti-reflective coating; 205 c-photoresist layer; 206 c-photoresist layer patterned; 206 b-bottom anti-reflective coating patterned; 206 a-dielectric anti-reflective coating patterned; 207-capacitor hole; 208-etching pillar; 209-first electrode layer; 210-dielectric layer; 211-second electrode layer; 212-conductive material; 40-semiconductor devices; D-first opening; and E-second opening.

DETAILED DESCRIPTION

Exemplary embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are illustrated in the accompanying drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided such that the present disclosure can be understood thoroughly and the scope of the present disclosure can be fully conveyed to those skilled in the art.

In the following description, numerous details are given to provide a more thorough understanding of the present disclosure. However it will be apparent to those skilled in the art that the present disclosure may be practiced without one or more of these details. In other examples, some technical features well known in the art are not described so as not to obscure the present disclosure. That is, all features of the actual embodiments are not described herein and well-known functions and structures are not described in detail.

In the drawings, dimensions of layers, regions and elements and relative dimensions thereof may be exaggerated for clarity. Throughout, the same reference numerals denote the same elements.

It should be understood that when an element or layer is referred to as being “on”, “adjacent to”, “connected to” or “coupled to” other elements or layers, it may be directly on, adjacent to, connected or coupled to the other elements or layers, or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on”, “directly adjacent to”, “directly connected to” or “directly coupled to” other elements or layers, there are no intervening elements or layers present. It should be understood that although the terms first, second, third, etc. may be employed to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only employed to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Therefore, without departing from the teachings of the present disclosure, a first element, component, region, layer or section discussed below may be represented as a second element, component, region, layer or section. Whereas the discussion of the second element, component, region, layer or section does not imply that the first element, component, region, layer or section is necessarily present in the present disclosure.

The terminology used herein is for the purpose of describing some embodiments only and is not intended to limit the present disclosure. As used herein, the singular forms of “a”, “one” and “said/the” are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and/or “including”, when used in this specification, determine the presence of the described features, integers, steps, operations, elements and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term “and/or” includes any and all combinations of related listed items.

Before the method for forming the semiconductor device provided by the embodiments of the present disclosure is introduced in detail, processes of forming the semiconductor device in the related technologies are first described.

FIGS. 1 a to 1 c are schematic structural diagrams showing processes of forming a semiconductor device according to one embodiment of the present disclosure. As shown in FIG. 1 a, a stack structure 101 is formed on a surface of a base substrate 100, and a first hard mask layer 102 and a second hard mask layer 103 are formed on a surface of the stack structure 101, where the second hard mask layer 103 has patterns in which capacitor holes are formed. The base substrate 100 includes a peripheral region 100-1 and an array region 100-2, where a pattern density of a capacitor hole pattern in the second hard mask layer on the array region 100-2 is greater than that of a capacitor hole pattern in the second hard mask layer on the peripheral region 100-1.

The formation process of the semiconductor device includes two pattern transfer processes. In the first pattern transfer process, the first hard mask layer is etched by means of the second hard mask layer to transfer the capacitor hole pattern in the second hard mask layer into the first hard mask layer. As shown in FIG. 1B, a first hard mask layer 102 a after the first etching is obtained by means of the first pattern transfer. During the first pattern transfer process, a thickness t1 of the second hard mask layer positioned on the array region 100-2 is less than a thickness t2 of the second hard mask layer positioned on the peripheral region 100-1 due to an etching load effect.

In the second pattern transfer process, the stack structure is etched by means of the first hard mask layer etched, to transfer the capacitor hole pattern into the stack structure 101; and the second hard mask layer 103 needs to be removed before the second pattern transfer is performed. As shown in FIG. 1 c, a capacitor pattern 101 a and a first hard mask layer 102 b after the second etching are formed in the second pattern transfer process, where the capacitor pattern 101 a has a top dimension B and a height D, and a distance between two adjacent capacitor patterns is S.

After the capacitor hole pattern is transferred into the stack structure, the first hard mask layer 102 b after the second etching also needs to be removed.

Because the pattern density of the capacitor hole pattern in the first hard mask layer on the array region 100-2 is greater than that of the capacitor hole pattern in the first hard mask layer on the peripheral region 100-1, in the first pattern transfer process and the second pattern transfer process, due to the etching load effect, a thickness t3 of the first hard mask layer positioned on the array region 100-2 is less than a thickness t4 of the first hard mask layer positioned on the peripheral region 100-1, and the first hard mask layer on the array region 100-2 and the first hard mask layer positioned on the peripheral region 100-1 have different roughness, which may even damage the stack structure 101 below the first mask layer 102 b, and thus adversely affect the performance of the semiconductor device.

FIG. 2 is a schematic flow diagram of a method for fabricating a semiconductor device according to another embodiment of the present disclosure. As shown in FIG. 2 , the method includes following steps.

Step 201: providing a semiconductor substrate having a first region and a second region.

As shown in FIG. 3 a, in some embodiments, the substrate includes a base substrate 200 and a stack structure 201 on the base substrate 200.

The stack structure 201 is configured to form a capacitor structure, and includes a first sacrificial layer 201 a, a first support layer 201 b, a second sacrificial layer 201 c and a second support layer 201 d stacked in sequence from bottom to top. The first sacrificial layer 201 a and the second sacrificial layer 201 c may be an oxide layer such as a silicon oxide layer. The first support layer 201 b and the second support layer 201 d may be silicon nitride layers.

In some embodiments, the base substrate includes an array region A and a peripheral region B, where the array region A is configured to form a memory device of a semiconductor memory cell, such as a memory capacitor, and the peripheral region B is configured to form a peripheral control circuit. Further, the first region is the memory array region A, and the second region is the peripheral circuit region B.

It should be noted that, the solutions of the present disclosure are not limited to the array region and the peripheral region, and the solutions of the present disclosure are applicable to patterning processes having different pattern densities.

In the embodiments of the present disclosure, a contact structure 200 a and an insulating layer 200 b covering the contact structure 200 a are formed in the base substrate 200. The contact structure 200 a is configured to electrically connect the capacitor structure formed. A material of the contact structure 200 a may be any conductive material, such as tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof.

Step 202: forming an initial mask layer on an upper surface of the substrate.

In the embodiments of the present disclosure, the initial mask layer may be any hard mask layer, for example, a polysilicon layer, a silicon nitride layer, or a spin-on carbon layer.

In some embodiments, the initial mask layer includes a second initial mask layer 202 and a first initial mask layer 203 a stacked in sequence from bottom to top. The first initial mask layer 203 a is an oxide material, and the second initial mask layer 202 is a polysilicon material.

Step 203: patterning the initial mask layer, forming a first pattern mask having a first height on the first region, and forming a second pattern mask having a second height on the second region, where a pattern density of the first pattern mask is greater than a pattern density of the second pattern mask, and the first height is greater than the second height.

In some embodiments, the first pattern mask may be a capacitor hole pattern or other patterns.

There are two patterning processes for the initial mask layer. In the first patterning process, the first pattern mask and the second pattern mask are formed first, and then part of the second pattern mask is removed. In the second patterning process, part of the initial mask layer on the second region is removed before the initial mask layer is not patterned, and then the first pattern mask and the second pattern mask are formed.

In some embodiments, when the first patterning process is used, the Step 203 of patterning the initial mask layer includes following steps.

Step 2031: providing a first pattern mask, forming the first pattern mask in the initial mask layer on the first region, and forming the second pattern mask in the initial mask layer on the second region, where the pattern density of the first pattern mask is greater than the pattern density of the second pattern mask.

In some embodiments, the Step 2031 may include following steps.

As shown in FIG. 3 b, the first initial mask layer is patterned based on the first pattern mask to form a first initial mask 203 a.

As shown in FIG. 3 c, the second initial mask layer 202 is etched based on the first initial mask 203 a, to form the first pattern mask 202 a and the second pattern mask 202 b.

As shown in FIG. 3 d, the first initial mask 203 a is removed.

It should be noted that, in the process of etching the second initial mask layer 202 by means of the first initial mask 203 a, due to the etching load effect caused by the different pattern densities of the patterns on the array region A and the peripheral region B, a residual thickness h1 of the first initial mask 203 a on the array region A is less than a residual thickness h2 of the first initial mask 203 a on the peripheral region B.

Step 2032: partially etching the second pattern mask 202 b, such that a height of the second pattern mask 202 b is less than that of the first pattern mask 202 a.

In some embodiments, the Step 2032 of partially etching the second pattern mask 202 b includes following steps.

As shown in FIG. 3 e, an intermediate dielectric material is deposited to form an intermediate dielectric layer 204 filling the first pattern mask 202 a and the second pattern mask 202 b.

In the embodiments of the present disclosure, the intermediate dielectric layer 204 may be a spin-on hard mask (SOH) layer, a spin-on carbon layer, or other hard mask layer; The intermediate dielectric layer 204 may be formed by means of any suitable deposition process.

As shown in FIG. 3 f, a second mask layer 205 is formed on the intermediate dielectric layer 204, where the second mask layer 205 includes a dielectric anti-reflective coating 205 a, a bottom anti-reflective coating 205 b and a photoresist layer 205 c stacked sequentially from bottom to top. In the embodiments of the present disclosure, the dielectric anti-reflective coating 205 a, the bottom anti-reflective coating 205 b and the photoresist layer 205 c may be formed by means of any suitable deposition process.

As shown in FIG. 3 g, a second pattern mask is provided, and a mask pattern exposing the second pattern mask is formed in the intermediate dielectric layer on the second region.

In the embodiments of the present disclosure, the photoresist layer 205 c on the peripheral region B is exposed by means of a preset second pattern mask C to obtain a photoresist layer 206 c patterned, and layer structures on the peripheral region B are exposed.

As shown in FIG. 3 h, a part of the second pattern mask 202 b is etched away based on the mask pattern.

In the embodiments of the present disclosure, a bottom anti-reflective coating 206 b, a dielectric anti-reflective coating 206 a, the intermediate dielectric layer 204 and a part of the second initial mask layer 202 above the peripheral region B are sequentially removed by etching downwards based on the photoresist layer 206 c patterned. Next, the photoresist layer 206 c and the bottom anti-reflective coating 206 b above the array region A are removed. That is, only the dielectric anti-reflective coating 206 a and the intermediate dielectric layer 204 are remained above the array region A.

As shown in FIG. 3 i, the intermediate dielectric layer 204 is removed.

In the embodiments of the present disclosure, the dielectric anti-reflective coating 206 a and the intermediate dielectric layer 204 remained above the array region A need to be removed, such that the first pattern mask 202 a and the second pattern mask 202 b are exposed. In this case, a height H1 of the first pattern mask 202 a is greater than a height H2 of the second pattern mask 202 b.

The height H1 of the first pattern mask 202 a positioned on the array region A is greater than the height H2 of the second pattern mask 202 b positioned on the peripheral region B, which may balance the etching load effect caused by different pattern densities during the etching process, such that the etching pillar is not damaged when the remaining first pattern mask 202 a is removed by subsequent etching, and thus no adverse effect is caused to capacitance of the capacitor structure formed.

In some embodiments, when the second patterning process is used, the Step 203 of patterning the initial mask layer includes following steps.

As shown in FIG. 3 j FIG. 3 k, a third pattern mask is provided, and a mask pattern exposing the initial mask layer of the second region is formed on the initial mask layer.

As shown in FIG. 3 l, the initial mask layer is partially etched based on the mask pattern, such that a height of the initial mask layer of the second region is smaller than that of the initial mask layer of the first region.

As shown in FIG. 3 m, a fourth pattern mask is provided, the first pattern mask is formed in the initial mask layer of the first region, and the second pattern mask is formed in the initial mask layer of the second region, where the pattern density of the first pattern mask is greater than the pattern density of the second pattern mask.

It should be noted that, the first pattern mask used in the first patterning process is the same as the fourth pattern mask used in the second patterning process, where the second pattern mask is the same as the third pattern mask. Moreover, neither the second pattern mask nor the third pattern mask is additional pattern mask. Instead, they are the pattern masks used in the previous fabrication process. That is, it is not required to provide additional pattern masks, where the pattern masks herein may be photomasks.

Step 204: etching the substrate based on the first pattern mask and the second pattern mask, transferring a pattern of the first pattern mask to the first region, and transferring a pattern of the second pattern mask to the second region.

In some embodiments, the first pattern mask 202 a is a capacitor hole pattern, and the contact structure 200 a corresponding to the capacitor hole pattern is formed in the base substrate 200.

In the embodiments of the present disclosure, Step S204 may include: etching the second support layer, the second sacrificial layer, the first support layer and the first sacrificial layer in sequence based on the first pattern mask, to transfer the capacitor hole pattern into the stack structure, and forming, in the stack structure, a plurality of capacitor holes and an etching pillar between the plurality of capacitor holes. The capacitor holes expose part of the contact structure.

As shown in FIG. 3 i and FIG. 3 n, based on the first pattern mask 202 a, the second support layer 201 d, the second sacrificial layer 201 c, the first support layer 201 b, the first sacrificial layer 201 a and part of the insulating layer 200 b are sequentially etched to form a plurality of capacitor holes 207 and an etching pillar 208 between adjacent two of the plurality of capacitor holes. Each capacitor hole 207 exposes one corresponding contact structure 200 a.

In some embodiments, after the capacitor holes are formed, the method for fabricating the semiconductor device further includes: removing the first pattern mask 202 a.

As shown in FIG. 3 o, after the capacitor holes 207 are formed, the first pattern mask 202 a remained on the array region A and the second pattern mask 202 b remained on the peripheral region B are removed by means of a dry etching process, such that a top surface of the etching pillar 208 is exposed.

In the embodiments of the present disclosure, the height H1 of the first pattern mask 202 a positioned on the array region A is greater than the height H2 of the second pattern mask 202 b positioned on the peripheral region B, which may balance the etching load effect caused by different pattern densities during the etching process, such that the etching pillar is not damaged when the remaining first pattern mask 202 a is removed by subsequent etching, and thus no adverse effect is caused to the capacitor structure formed, thereby reducing sources of defects.

In some embodiments, after the first pattern mask 202 a is removed, the method for fabricating the semiconductor device further includes: processing the etching pillar to form the capacitor structure.

In some embodiments, the processing the etching pillar to form the capacitor structure includes following steps.

Step S20: forming a first electrode layer on an inner wall of each of the plurality of capacitor holes and a surface of the etching pillar respectively.

The first electrode layer may be a titanium nitride layer.

Step S21: forming a first opening in the second support layer.

Step S22: removing the second sacrificial layer by means of the first opening.

Step S23: forming a second opening in the first support layer.

Step S24: removing the first sacrificial layer by means of the second opening

As shown in FIG. 3 p, a first electrode layer 209 is formed on the inner wall of the capacitor hole 207 and the surface of the etching pillar; a first opening D is formed in the second support layer, and the second sacrificial layer is removed through the first opening D; and a second opening E is formed in the first support layer, and the first sacrificial layer is removed through the second opening E.

In the embodiments of the present disclosure, the first opening D and the second opening E may be formed by means of a dry etching technique such as a plasma etching technique.

In the embodiments of the present disclosure, the second sacrificial layer and the first sacrificial layer may be removed by means of a wet etching technique, for example, by using an etching solution such as sulfuric acid, hydrofluoric acid, and nitric acid.

Step S25: sequentially depositing a dielectric layer and a second electrode layer on a surface of the first electrode layer to form the capacitor structure.

As shown in FIG. 3 q, a dielectric layer 210 and a second electrode layer 211 are formed on the surface of the first electrode layer 209. In the embodiments of the present disclosure, the dielectric layer 210 may be a zirconia layer and/or an alumina layer, or may be other high dielectric constant material layer. The second electrode layer 211 may be the same as or different from the first electrode layer 209.

In some embodiments, the method of forming the semiconductor device further includes: depositing a conductive material between the second electrode layers. The conductive material may be polysilicon or any other suitable conductive material such as tungsten, cobalt, or doped polysilicon.

According to the method for fabricating the semiconductor device provided by the embodiments of the present disclosure, different mask thicknesses are formed in regions where the masks have different pattern densities, to balance the etching load effect brought by the different pattern densities in an etching process, improve etching stability of the high aspect ratio structure, and reduce the sources of the defects, thereby improving integrity and stability of the capacitor pattern, and improving performance of the semiconductor device.

In addition, the embodiments of the present disclosure also provide a semiconductor device, which is fabricated by means of the method for fabricating the semiconductor device provided in the above embodiments. FIG. 4 is a cross-sectional view of a semiconductor device according to one embodiment of the present disclosure. As shown in FIG. 4 , the semiconductor device 40 includes a base substrate 200 and a capacitor structure, where the base substrate 200 includes a contact structure 200 a and an insulating layer covering the contact structure 200 a, and the contact structure 200 a is configured to electrically connect the capacitor structure formed.

In the embodiments of the present disclosure, the base substrate 200 includes an array region A and a peripheral region B, and the capacitor structure is positioned on the surface of the array region A of the base substrate 200.

With continued reference to FIG. 4 the capacitor structure includes a first electrode layer 209, a dielectric layer 210 and a second electrode layer 211 stacked in sequence, and a conductive material 212 is filled between adjacent second electrode layers 211.

In the embodiments of the present disclosure, the capacitor structure has a cup-shaped structure, and the capacitor structure further includes a first support layer 213 and a second support layer 214 arranged in parallel. The first support layer 213 is provided at a middle periphery of the capacitor structure, the second support layer 214 is provided at a top periphery of the capacitor structure, and the first support layer 213 and the second support layer 214 are jointly configured to support the capacitor structure.

In some embodiments, the thickness h3 of the second support layer 214 is greater than the thickness h4 of the first support layer 213, such that a better support effect can be achieved.

The method for fabricating the semiconductor device in this embodiment of the present disclosure is similar to the method for fabricating the semiconductor device in the above-mentioned embodiments. Therefore, reference is made to the above-mentioned embodiments for technical features not disclosed in detail in this embodiment of the present disclosure, and detailed descriptions thereof are omitted here.

According to the semiconductor device provided by the embodiments of the present disclosure, the etching load effect brought by the different pattern densities in an etching process is balanced by different mask thicknesses to improve the etching stability of the high aspect ratio structure, and reduce the sources of the defects, thereby improving integrity and stability of the capacitor pattern, and improving the performance of the semiconductor device.

From several embodiments provided in the present disclosure, it should be understood that the disclosed apparatus and method may be implemented by means of non-objected manners. The apparatus embodiments described above are merely exemplary. For example, the unit partition is merely a logic functional partition. In actual implementation, additional manners of partitioning may be available. For another example, a plurality of units or components may be combined or integrated into another system, or some features may be ignored or not executed. In addition, the displayed or discussed mutual couplings or direct couplings between constituent parts may be implemented by using some interfaces.

The units described as separate components may or may not be physically separate, and components displayed as units may or may not be physical units, may be positioned in one position, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the objectives of the solutions of this embodiment.

The features disclosed in several methods or apparatus embodiments provided in the present disclosure may be arbitrarily combined without conflict to obtain new method embodiments or apparatus embodiments.

The above-mentioned embodiments are merely some embodiments of the present disclosure, but the protection scope of the embodiments of the present disclosure is not limited thereto. Any variation or substitution easily conceivable to a person of ordinary skills in the art within the technical scope disclosed in the embodiments of the present disclosure shall fall within the protection scope of the embodiments of the present disclosure. Therefore, the protection scope of the embodiments of the present disclosure shall be subject to the protection scope of the claims. 

What is claimed is:
 1. A method for fabricating a semiconductor device, comprising: providing a semiconductor substrate having a first region and a second region; forming an initial mask layer on an upper surface of the substrate; patterning the initial mask layer, forming a first pattern mask having a first height on the first region, and forming a second pattern mask having a second height on the second region, a pattern density of the first pattern mask being greater than a pattern density of the second pattern mask, and the first height being greater than the second height; and etching the substrate based on the first pattern mask and the second pattern mask, transferring a pattern of the first pattern mask to the first region, and transferring a pattern of the second pattern mask to the second region.
 2. The method according to claim 1, wherein the first region is a memory array region, and the second region is a peripheral circuit region.
 3. The method according to claim 1, wherein the patterning the initial mask layer comprises: providing a first pattern mask, forming the first pattern mask in the initial mask layer on the first region, and forming the second pattern mask in the initial mask layer on the second region, the pattern density of the first pattern mask being greater than the pattern density of the second pattern mask; and partially etching the second pattern mask, such that a height of the second pattern mask is less than a height of the first pattern mask.
 4. The method according to claim 3, wherein the initial mask layer comprises a second initial mask layer and a first initial mask layer stacked sequentially from bottom to top; and the forming the first pattern mask in the initial mask layer on the first region, and forming the second pattern mask in the initial mask layer on the second region comprises: patterning the first initial mask layer based on the first pattern mask to form a first initial mask; etching the second initial mask layer based on the first initial mask to form the first pattern mask and the second pattern mask; and removing the first initial mask.
 5. The method according to claim 3, wherein the partially etching the second pattern mask comprises: depositing an intermediate dielectric material to form an intermediate dielectric layer filling the first pattern mask and the second pattern mask; providing a second pattern mask, and forming a mask pattern exposing the second pattern mask in the intermediate dielectric layer on the second region; etching and removing part of the second pattern mask based on the mask pattern; and removing the intermediate dielectric layer.
 6. The method according to claim 1, wherein the patterning the initial mask layer comprises: providing a third pattern mask, and forming, on the initial mask layer, a mask pattern exposing the initial mask layer of the second region; partially etching the initial mask layer based on the mask pattern, such that a height of the initial mask layer of the second region is smaller than a height of the initial mask layer of the first region; and providing a fourth pattern mask, forming the first pattern mask in the initial mask layer of the first region, and forming the second pattern mask in the initial mask layer of the second region, the pattern density of the first pattern mask being greater than the pattern density of the second pattern mask.
 7. The method according to claim 1, wherein the substrate comprises a base substrate and a stack structure on the base substrate; wherein the stack structure comprises a first sacrificial layer, a first support layer, a second sacrificial layer and a second support layer stacked in sequence from bottom to top.
 8. The method according to claim 7, wherein the first pattern mask is a capacitor hole pattern, and a contact structure corresponding to the capacitor hole pattern is formed in the base substrate.
 9. The method according to claim 8, wherein the etching the substrate based on the first pattern mask and the second pattern mask, and transferring the pattern of the first pattern mask to the first region comprises: etching the second support layer, the second sacrificial layer, the first support layer and the first sacrificial layer in sequence based on the first pattern mask, to transfer the capacitor hole pattern into the stack structure, and forming, in the stack structure, a plurality of capacitor holes and an etching pillar between adjacent two of the plurality of capacitor holes; wherein the plurality of capacitor holes expose part of the contact structure.
 10. The method according to claim 9, further comprising: removing the first pattern mask after the plurality of capacitor holes are formed.
 11. The method according to claim 10, further comprising: processing the etching pillar to form a capacitor structure.
 12. The method according to claim 11, wherein the processing the etching pillar to form the capacitor structure comprises: forming a first electrode layer on an inner wall of each of the plurality of capacitor holes and a surface of the etching pillar respectively; forming a first opening in the second support layer; removing the second sacrificial layer by means of the first opening; forming a second opening in the first support layer; removing the first sacrificial layer by means of the second opening; and sequentially depositing a dielectric layer and a second electrode layer on a surface of the first electrode layer to form the capacitor structure.
 13. A semiconductor device, wherein the semiconductor device is fabricated by means of the method for fabricating the semiconductor device according to claim 1, and the semiconductor device at least comprises a base substrate and a capacitor structure; wherein the base substrate comprises a contact structure; and the capacitor structure is positioned on a surface of the base substrate and in contact with the contact structure. 